LEE-128G032B www.vishay.com vishay dale revision: 07-dec-12 1 document number: 37088 for technical questions, contact: displays@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 led display modules 128 x 32 graphics display with drive electronics and + 5 v hc cmos level video interface red led modules, normal br ightness, single board construction , rohs-compliant the LEE-128G032B is an led replacement for the popular apd-128g032 plasma display module. it is designed to offer high brightness and superi or viewing characteristics in a slim package. this display is ideal for low to medium level information content and is ideal for applications such as arcade games, process cont rol, pos terminals, medical equipment, message centers and atm machines. the LEE-128G032B led display offers high contrast, wide viewing angle, and long distance readability. it emits a bright red color which catches the attent ion of the viewer, but is yet comfortable to the eye. the LEE-128G032B led display has a video type interface and is driven in a standard row/column refresh method. pixel data is clocked for a row, and rows are scanned sequentially. signals are presented for serial data , dot clock , column latch , row data , row clock and display enable . the serial data is entered with the dot clock up to frequencies as high as 8 mhz. after a row of 128 pixels is clocked in, the column latch signal is toggled and the data is latched. at the time the data is latched, the di splay is briefly disabled using the display enable signal, then the row pointer is advanced with the row clock signal. once each frame the row data must be asserted to synchronize the column serial data with the beginning row. the recommended scanning frequency is approximately 70 hz, but may be as high as 200 hz. note ? recommended operating voltages, all maximums are absolute maximum features ? led replacement for the popular apd-128g032 plasma display module ? + 5 v hc cmos level video interface ? large characters ? highly visible for long distance viewing ? > 30:1 contrast ratio ? bright red color ? slim profile ? reduced power and brightness version ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 electrical specifications voltage(s) required: + 5 v dc (v cc ) power required (fully lit): typ. = 5.5 w, max. = 6.5 w optical specifications viewing area: 12.75" [323.8 mm] w x 3.15" [80.01 mm] l character size (5 x 7): 0.65" [16.51 mm] h x 0.45" [11.43 mm] w pixel size: 0.063" [1.6 mm] h x 0.031" [0.8 mm] w pixel pitch: 0.100" [2.54 mm] luminance: 100 ft-l minimum color: bright red viewing angle: > 150 environmental specifications operating temperature: - 40 c to + 85 c storage temperature: - 40 c to + 85 c relative operating humidity: to 95 % non-condensing mechanical shock: 30 g vibration: 3 g operating altitude: 10 000 ft standard electrical specifications description symbol min. typ. max. units logic and led drive voltage v cc + 4.5 + 5.0 + 5.5 v dc logic and led drive current (fully lit) i cc -1.11.3a dc logic 1 input v ih 0.7 v cc --v dc logic 0 input v il - - 0.3 v cc v dc dimensions in inches [millimeters] 0.250 max. 0.062 0.75 max. component height 7.25 14.80 0.150 7.25 4.625 4.925 0.150 3.15 viweing area 0.889 12.68 viewing area pin 1 of j1 pin 1 of j2 0.150 mounting hole s (6 x) 1.057
LEE-128G032B www.vishay.com vishay dale revision: 07-dec-12 2 document number: 37088 for technical questions, contact: displays@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 interface signal description dot clock - this signal enters the serial data on each low to high transition. a total of 128 dot clock transitions must be present for each line of column/anode data. serial data - this signal presents the pixel data in positive logic format. a logic one repre sents a lit pixel and a logic zero represents an extinguished pixel. data is entered from right to left. the first pixel data entered will re present the left most pixel in the row. column latch - this signal latches the pixel data into the driver outputs. when the column latch signal goes to logic one the data entered previously wi ll fall through to the driver outputs. when the signal returns to a logic zero the data is latched and the shift register is now ready to accept the next row of data. must be held low while entering new serial data . display enable - this signal enables the output drivers. using a duty cycle control, this signal may also be used for intensity control. the display enable must be at logic zero before the column latch signal transitions. to avoid display blurring, the row clock signal should also transition while display enable is a logic zero. row data - this signal is the first line marker for the scan. this input should be held high to correspond to the first row of pixel data. row clock - this signal clocks row data on the falling edge. the row clock signal is repetitive and must be present for proper scanning of the display module. the LEE-128G032B has an unique input protection circuit that assures the colu mn drivers stay blanked on power up. the protection circuit unblanks the column drivers when the row clock signal begins (i.e the display begins scanning). pin description j2 - power connector molex 26-48-1045 or equivalent. mates with tyco amp 3-640428-8, or molex 09-50-3041 housing with 08-50-0106 socket cr imp terminals or equivalent. pin signal description 1v cc logic and led drive supply 2v cc logic and led drive supply 3 gnd ground 4 gnd ground j1 - data connector fci 75869-102lf or equivalent. mates with tyco amp 1658621-2 or equivalent pin description pin description 1 display enable 2 ground 3 row data 4 ground 5 row clock 6 ground 7 column latch 8 ground 9 dot clock 10 ground 11 serial data 12 ground 13 no connection 14 ground logic and data timing parameter min. typ. max. units t 1 100 - - ns t 2 5--s t 3 1--s t 4 - 70 200 hz t 5 25 - - ns t 6 75 - - ns t 7 75 - - ns ordering information description part number display, driver electronics and + 5 v hc cmos interface led-128g032b j1 data connector kit (2 pcs. recommended) 280105-08 j2 power connector kit 280108-16 row clock column latch display ena b le row data t 4 display ena b le 2 1 0303101 s erial data 2 1 0 126 127 1 s t bit of row will appear in left mo s t column t 2 row clock 230310 1 1 0 t 3 t 1 t 5 dot clock po s itive edge x 128 t 6 t 7
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